Soft errors from radiation particles, which are also known as single event upsets (SEUs), are a large concern in high reliability applications. In chips with even moderate amount of unprotected SRAM arrays, SEUs can dominate the error rate. SEUs in latches are a growing concern in terrestrial applications for the 90 nm semiconductor technology and beyond. SEUs are a greater concern in high radiation applications, such as aerospace or military applications.
Many known circuit techniques reduce the SEU sensitivity of a circuit with an accompanying area or performance penalty. Fault tolerant systems can detect most or all SEUs and correct some of them, at the expense of greater complexity and often with performance penalties. At a given lithographic node, SOI circuits have lower SEU rates than comparable bulk circuits; the SEU rate of SOI SRAMs is often less than 20 percent of that of comparable bulk SRAMs. SOI semiconductor devices have lower SEU rate because the volume of the semiconductor material that can collect charges generated by ionizing radiation is confined above the BOX. Bulk semiconductor devices have a much higher SEU rate because the volume of the semiconductor material sensitive to ionizing radiation extends at least as deep as the thickness of doped wells. In this regard, SOI substrates offer greater radiation immunity than bulk substrates.
According to hybrid orientation technology (HOT), a portion of a semiconductor substrate has an SOI structure with one surface orientation and another portion of the same semiconductor structure has a bulk substrate structure with another surface orientation. Such a semiconductor substrate is herein referred to as a “HOT substrate.” HOT substrates have been used to build MOSFETs of different types on different orientations of semiconductor surfaces with resulting substantial gains in device performance. According to HOT, the NFETs and PFETs are fabricated in regions with different crystal orientation to optimize the mobility of minority carriers in the channel for both devices, i.e. NFETs are in a region of (100) crystal orientation to maximize the mobility of electrons, while PFETs are in a region of (110) crystal orientation to maximize the mobility of holes. A region of one crystal orientation, which is used for devices of one polarity (either NFETs or PFETs), is located in the SOI portion of the semiconductor substrate and another region of the other crystal orientation, which is used for devices of the other polarity (either PFETs or NFETs), is located in the bulk portion of the semiconductor substrate.
Due to the inherently higher SEU rate of devices built on a bulk substrate, the MOSFET devices built in the bulk portion of the semiconductor substrate are as prone to high SEU rates as equivalent devices built on a bulk substrate.
Therefore, there exists a need for structures and methods for reducing SEU rates on CMOS devices built in the bulk portion of a HOT substrate.
Also, if PFETs are built in the bulk portion of a HOT wafer with a P-handler substrate, the parasitic bipolar transistor components and the parasitic resistors of the structure containing of N+ contact to the N− well, PFETs built on the N− well, N− well itself, and the P− substrate forms a latchup circuitry as in such devices built on a bulk P− substrate. Protection against latchup for the MOSFET devices built in the bulk portion of the semiconductor substrate is desired.
Therefore, there exists a need for providing protection against latchup for PFETs built in the bulk portion of a HOT substrate.